Responsible for multi-module collaboration verification of SoC chips (e.g., NPU+ISP joint processing), resource contention and scheduling optimization, and long-term stability testing under various combinations and stress conditions.

Design test plans and strategies.

Develop test cases, technical documents and test reports; promote the standardization of test processes.

Develop or apply automation tools to improve test efficiency.

Familiar with SoC chip architecture and test methods; proficient in system integration testing among multiple modules and various functional combinations.

Understand common application solutions of SoC chips; have relevant development or testing experience.

Proficient in C/C++/Python with clear and standard coding practices.

Rigorous logical thinking; able to decompose complex issues such as multi-core resource contention and abnormal power consumption.

Strong cross-team collaboration skills; sensitive to AI chip technology trends and capable of rapid learning of emerging technologies.

Experience in edge computing scenarios and edge-side AI deployment is preferred.